IEEE

Benchmarking of FERAM-Based Memory System by Optimizing Ferroelectric Device Model

Abstract: We present a framework for design technology co-optimization (DTCO) of the main memory system with one transistor-one capacitor (1T1C) ferroelectric random access memory (FERAM) as an ...
GitHub

SOSP 25 | DiffKV: Differentiated Memory Management for Large Language Models with Parallel KV Compaction

Current mainstream KV cache optimization techniques (quantization and pruning) suffer from "one-size-fits-all" limitations and cannot fully exploit the fine-grained differences within the KV cache.
IEEE

HUNBN, a 16-nm Digital In-Memory-Compute SoC for Edge CNN Application Achieving 24 TOPs/W (4b) at System Level

Abstract: This work presents HUNBN, a fully digital in-memory-compute (DIMC) system-on-chip (SoC) implemented using 16-nm FinFET CMOS technology. Designed for edge convolution neural network (CNN) ...
techxplore

Next-generation memory: Tungsten-based SOT-MRAM achieves nanosecond switching and low-power data storage

The ability to reliably switch the direction of magnetic alignment in materials, a process known as magnetization switching, is known to be central to the functioning of most memory devices. One known ...