GitHub

intel-de10-lite

A 4-bit arithmetic calculator built in Verilog on the Intel DE10-Lite FPGA. Performs addition and two’s-complement subtraction with results displayed on seven-segment LEDs.
IEEE

Architecture Generator for Type-3 Unum Posit Adder/Subtractor

Abstract: This paper is aimed towards the hardware architecture aspect of a recently proposed posit number system under type-3 unum (universal number system). Here, an algorithmic flow for the posit ...
GitHub

MIPS Processor Implementation in Verilog

This project focuses on the design and implementation of a MIPS processor using Verilog as part of the Computer Architecture Laboratory. The objective was not only to build processor capable of ...
IEEE

Improving LLM-Based Verilog Code Generation with Data Augmentation and RL

Abstract: Large language models (LLMs) have recently attracted significant attention for their potential in Verilog code generation. However, existing LLM-based methods face several challenges, ...