EDN

Playing it cool

The semiconductor industry has long relied on scan ATPG (automatic test pattern generation) tools instead of functional test to create stimulus-response patterns with very high fault coverage. But ...
Semiconductor Engineering

Can Your ATPG Do This? Cut Defects Escaping Detection With ML

Chipmakers worldwide consider Automatic Test Pattern Generation (ATPG) their go-to method for achieving high test coverage in production. ATPG generates test patterns designed to detect faults in the ...
Semiconductor Engineering

Squeezing Out More Test Compression

The trend in semiconductors leads to more IC test data volume, longer test times, and higher test costs. Embedded deterministic test (EDT) has continued to deliver more compression, which has been ...
Design-Reuse

Faster and Fewer Patterns with Breakthrough ATPG to the Rescue

New semiconductor technologies like FinFETs are giving rise to new types of fault effects not covered by standard stuck-at and at-speed tests. Automatic test pattern generation (ATPG) tools perform ...
EDN

Smart test for nanometer designs

When semiconductor devices had geometries of 0.18 microns and larger, most defects manifested themselves as static faults. Test strategies based on stuck-at fault-model scan patterns and standard ...
Electronic Design

Where Is DFT Heading?

Design for test (DFT) has been around since the 1960s. The technology was developed to reduce the cost of creating a successful test for an IC. Scan design, fault models, and automatic test pattern ...
Design-Reuse

SOC: Submicron Issues -> Heading off test problems posed by SoC

Ron Press, Technical Marketing Manager, ATPG Products, Janusz Rajski, Chief Scientist and Business Unit Manager, ATPG Product Group, Mentor Graphics Corp., Wilsonville, Ore. A system-on-chip is a ...