EDN

Partitioning an ASIC Design into Multiple FPGAs

Most of today's system-on-chip (SoC) designs rely on field-programmable gate arrays (FPGAs) as a way to accelerate verification, start software development early and validate the whole system before ...
EDN

HDL-design challenges and philosophies for real-world ASIC implementations

New requirements for the MAC (medium-access control) and PHY (physical-layer interface) of a wireless-communications system can pose significant challenges for system designers looking to quickly get ...
Semiconductor Engineering

Connecting System-Level Flows To Implementation Tools

With the complexity explosion occurring in SoC design today, there is a relentless force to push design decisions further up in terms of abstraction. Resolving issues at the gate level is not possible ...
Electronic Design

ASIC Handoff Gets Physical As Front And Back Ends Converge

True or false: ASIC design follows a very straightforward path that begins with high-level architectural definition. It proceeds through RTL design and preliminary floorplanning. After synthesis, the ...
Design-Reuse

MAZeT offers Interbus-IP for customized FPGA and ASIC implementation

Jena -- March 19 2009 - MAZeT GmbH offers IP cores for the Interbus protocol (SUPI4 / Phoenix Contact) for implementation in FPGAs and ASICs. The protocol chip for serial communication interfaces in ...
Business Wire

Faraday Announces Plans to Develop Arm-Based 64-Core SoC on Intel 18A Technology

HSINCHU, Taiwan--(BUSINESS WIRE)--Faraday Technology Corporation (TWSE: 3035), a leader in ASIC design services and IP solutions, announces its collaboration with Arm and Intel in spearheading the ...
Business Wire

Faraday Joins Intel Foundry Accelerator Design Services Alliance to Target Advanced Applications

HSINCHU, Taiwan--(BUSINESS WIRE)--Faraday Technology Corporation (TWSE: 3035), a leader in ASIC design services and IP solutions, announces joining the Intel Foundry Accelerator Design Services, ...
Electronic Design

Changing Requirements for ASIC Design

It’s a changing world. In 1851, the headline of an editorial in an Indiana newspaper urged readers to “Go West, Young Man!” Fast forward 150 years, and you ...
Design-Reuse

Magma and ChipX Extend Integrated RTL-to-GDSII Design Flow to Next-Generation Structured ASIC Designs

Magma Blast Create SA, Blast Fusion SA and ChipX CX6000 Structured ASIC combine to reduce cost and cycle time of high-performance designs SANTA CLARA, Calif., Nov. 9, 2005 - ChipX, the structured ASIC ...
Semiconductor Engineering

FPGA Design Tradeoffs Getting Tougher

FPGAs are getting larger, more complex, and significantly harder to verify and debug. In the past, FPGAs were considered a relatively quick and simple way to get to market before committing to the ...
SDxCentral

Marvell Adds Custom ASICs to Semiconductor Portfolio

ASICs, for all the advantages they offer, are an expensive and time-consuming endeavor. But do they have to be? That's the question semiconductor vendor Marvell has posed with the launch of its custom ...